(1) Field of the Invention
This invention relates to methods used to fabricate semiconductor devices, and more specifically a process used to fabricate high performance logic devices and low cost memory devices, on a single semiconductor chip.
(2) Description of Prior Art
The semiconductor industry is continually striving to increase device performance, while still maintaining, or even reducing the cost of these same devices. Micro-miniaturization or the ability to create semiconductor devices with sub-micron features, has allowed the performance, and the cost objectives, to be partially realized. The use of sub-micron features result in a decrease in performance degrading, parasitic capacitances, thus allowing performance improvements to be realized. In addition the use of sub-micron features allows smaller semiconductor chips to be created, with the smaller chips still offering device densities comparable to device densities achieved with larger chips, thus allowing a greater number of chips to be realized from a specific size starting semiconductor substrate, thus reducing processing costs.
Another direction taken by the semiconductor industry, in an attempt to reduce cost while still improving device performance, has been the integration of logic devices, and memory devices, on the same semiconductor chip. This integration improves performance by decreasing undesirable delays that occur between memory devices, located on one semiconductor chip, and logic devices, located on a different chip. In addition the processing costs for integrating memory and logic devices on the same semiconductor chip, are reduced due to the sharing of specific process steps, used to fabricate both types of devices.
Efforts have been ongoing by the semiconductor industry, in attempting to incorporate both logic and memory requirements on a single semiconductor chip. Dennison, in U.S. Pat. No. 5,292,677, describes a process for integrating complimentary metal oxide semiconductor, (CMOS), devices, with dynamic random access memory, (DRAM), devices, on a single semiconductor chip. However that invention does not share as many processing steps needed to realize significant cost reductions, nor does it offer a process needed for high performance logic devices. This invention will describe an integrated process, which features high performance CMOS devices, realized via many innovations such as the use of gate insulator layers, thinner than the gate insulator layers used for the DRAM devices. It will also feature the use of conductive silicide layers for source and drain regions of the CMOS devices, formed using a process sequence that reduces a possible bridging mechanism between gate structures and substrate. In addition this new process, for forming high performance logic, and embedded memory devices, on a single semiconductor chip, will be practiced using many process sequences, shared by both type devices, with the addition of only two photolithographic masking procedures, added to the CMOS logic process sequence, which enables improved performance of the logic region to be realized while and still achieve cost reductions.